1. Field of the Invention
The present invention relates to a method of manufacturing a circuit substrate and a method of manufacturing an electronic parts packaging structure and, more particularly, a method of manufacturing a circuit substrate onto which electronic parts such as a semiconductor chip, and the like are mounted and a method of manufacturing an electronic parts packaging structure for mounting an electronic parts on the circuit substrate.
2. Description of the Related Art
In the prior art, there exists a circuit substrate on which the electronic parts such as the semiconductor chip, and the like are mounted. In such a circuit substrate, the multi-layered wiring layers are built-in, and the connection pads to which the semiconductor chip is electrically connected are provided to the uppermost portion. The plating layer made of the nickel (Ni)/gold (Au) layer, or the like is provided to the upper portion of the connection pad. For example, in case the semiconductor chip and the connection pads on the circuit substrate are connected by wire bonding, sometimes the plating layer of the connection pad is formed by electroplating to enhance the hardness of the connection pad.
A method of forming an electroplating layer on connection pads on a circuit substrate in the prior art is shown in FIG. 1 and FIG. 2. FIG. 2 is an enlarged plan view showing a portion indicated as a B portion in FIG. 1. As shown in FIG. 1, areas A as respective circuit substrates are defined on a substrate 100, and predetermined multi-layered wiring layers (not shown) are formed in each area A, respectively. Also, a plurality of plating power-supply lines 102 are provided in the substrate 100 to define respective areas A. Each plating power-supply line 102 is connected to a plating power-supply portion 104 provided to an outer peripheral portion of the substrate 100 like a ring. Also, as shown in FIG. 2, a plurality of plating lead wires 108 are connected to the plating power-supply lines 102, and the plating lead wires 108 are connected electrically to each connection pad 106, respectively.
In this manner, each connection pad 106 is connected electrically to the plating power-supply portion 104 via the plating lead wires 108 and the plating power-supply lines 102. Then, when a current is supplied from the plating power-supply portion 104, an electroplating layer is formed on the connection pads 106 by electroplating. Then, the substrate 100 is cut so that respective circuit substrates may be obtained, and then the plating power-supply lines 102 and the plating power-supply portion 104 are discarded.
Meanwhile, in the semiconductor chip, such as a CPU, or the like, because the number of connection portions is increased following upon an increase of the I/0 number, the number of connection pads on the circuit substrate is also increased and thus a pitch between the connection pads is made narrower. When a pitch between the connection pads on the circuit substrate is reduced smaller, it is difficult to provide a predetermined number of plating power-supply lines between the connection pads in parallel with each other. As a result, the connection pads on which the electroplating layer cannot be formed are generated.